Standard cells are designed to implement logic functions each by way of a dedicated electrical circuit including a power rail, a ground rail, signal gates and wire segments to internally interconnect their signal gates (hereinafter referred to as “intra cell signal wiring”). Standard cells are intended to be embodied in an IC's transistor embedded semiconductor substrate, and its interconnect structure which includes a polysilicon layer, and one or more interconnect metal layers. Simple standard cells having only a few signal gates require relatively little intra cell signal wiring embodied as a few wire segments which can be conveniently routed through an IC's polysilicon layer and the lowermost interconnect metal layer immediately overlying its polysilicon layer hereinafter denoted M1. Standard cells have a uniform height spanning a predetermined number of imaginary horizontal routing tracks so that they can be deployed side-by-side to constitute horizontal standard cell rows spanning the same number of imaginary horizontal routing tracks.
In accordance with conventional standard cell IC design methodology, a so-called “place and route” software accesses a computerized standard cell library to initially place standard cells in standard cell rows in accordance with a predetermined netlist, and then determines the wire segments to interconnect signal gates of different standard cells within the same or different standard cell rows (hereinafter referred to as “inter cell signal wiring”). To improve area utilization, standard cell rows are typically arranged in pairs with a common M1 ground rail between a pair of inverted juxtaposed standard cell rows. To reduce the complexity of inter cell signal wiring, inter cell signal wiring wire segments are preferably either entirely horizontal or vertical oriented on any particular high interconnect metal layer M2, M3, M4, and above, and preferably horizontal and vertical oriented on alternate high interconnect metal layers.
More complex standard cells require more intra cell signal wiring wire segments which whilst they could still theoretically be solely routed through an IC's polysilicon layer and its M1 they would lead to undesirably wide footprints since they are constrained in their height, thereby reducing area efficiency. To overcome this, it has been proposed to additionally utilize a high interconnect metal layer dedicated to having horizontal oriented wire segments for intra cell signal wiring purposes as opposed to being previously exclusively restricted for inter cell signal wiring purposes. However, this may lead to many, and in the worst possible scenario all, of the selected high interconnect metal layer's routing tracks having one or more intra cell signal wiring wire segments somewhere therealong, thereby undesirably militating against its availability for inter cell signal wiring purposes.